The present invention relates to electronic device manufacture, and more particularly, but not exclusively, relates to integrated circuit device manufacturing techniques that minimize electrical leakage caused by silicidation.
One common failure mechanism experienced during the manufacture of integrated circuit devices with planar insulated gate field effect transistors (IGFETs) is electrical bridging of an oxide spacer situated between the transistor gate and its corresponding source or drain. This type of defect often manifests itself as low resistance leakage that prevents proper operation of the affected IGFET. Typically, bridging of the oxide gate spacer occurs as an unintended consequence of the formation of silicide contact areas along silicon surfaces of the device.
Generally, silicide formation includes placing a metal blanket in contact with selected silicon surface regions, and then heating the device to cause a reaction between the silicon and metal. A silicide film results from this reaction along the regions of silicon/metal contact. During such silicidation processing, one possible side-effect is the occurrence of oxide-metal reactions along the oxide surface of a gate spacer. These reactions are thought to occasionally lead to the formation of a thin silicide film over the spacer, sometimes resulting in a low resistance pathway or electrical short between the gate and a source or drain region. Further, the silicide compound formed on a silicon region adjacent the spacer sometimes overflows causing a low resistance pathway or electrical short. This problem becomes even more troublesome as integrated circuit devices are scaled down to provide critical dimensions deep in the submicron range.
One way to address this problem is to reduce the thickness of the metal blanket placed in contact with the spacer. Unfortunately, an unacceptably high sheet resistance of desired silicide regions may result when the thickness of the metal blanket contacting silicon is correspondingly reduced. Thus, there is a demand for better techniques to manufacture electronic devices. These techniques preferably include the reduction of gate spacer bridging as an unwanted side-effect of silicide formation.